#ifndef _SAMPLE_COMMON_H_
#define _SAMPLE_COMMON_H_
#include "_fr.h"
#include "library_conf.h"
#include "config.h"

/* clear watchdog timer1 */
#define CLEAR_WATCHDOG_TIMER1()	\
{ \
	WDTCPR1 = 0xa5; \
}

/* interrupt mask */
#define INTERRUPT_MASK    (GDC_MCNT_REG_IST_MASK_DRAW_ERR    |\
                           GDC_MCNT_REG_IST_MASK_DRAWCMD_INT |\
                           GDC_MCNT_REG_IST_MASK_VSYNC       |\
                           GDC_MCNT_REG_IST_MASK_SYNCERR)

/*========================================================================================================================
Remarks: The modification of the following display clock timing parameter requires rebuild "DispLibAPIL01R02" library for activation.
=======================================================================================================================*/
#ifdef GDC_HVGA
/* QVGA */
#define DISP_HTP    (610)
#define DISP_HSP    (525)
#define DISP_HSW    (40)
#define DISP_HDP    (480)
#define DISP_VTR    (300)
#define DISP_VSP    (288)
#define DISP_VSW    (2)
#define DISP_VDP    (272)
#define DISP_DCM1   (0x00000900)
#define DISP_DCM3   (0x000)
#endif /* GDC_QVGA */

/*========================================================================================================================
Remarks: The modification of the following display clock timing parameter requires rebuild "DispLibAPIL01R02" library for activation.
=======================================================================================================================*/
#ifdef GDC_QVGA

#if (CHOOSE_LCD == LCD_35371A_565_3_5)
#define DISP_HTP    (270)
#define DISP_HSP    (255)
#define DISP_HSW    (10)
#define DISP_HDP    (240)
#define DISP_VTR    (350)
#define DISP_VSP    (335)
#define DISP_VSW    (10)
#define DISP_VDP    (320)


#define DISP_DCM1   (0x00001100)
#define DISP_DCM3   (0x100)
/////////////////////////////////////////////////
#elif (CHOOSE_LCD == LCD_56999_888_3_5)

#define DISP_HTP    (424)
#define DISP_HSP    (368)
#define DISP_HSW    (20)
#define DISP_HDP    (320)	//

#define DISP_VTR    (276)	//
#define DISP_VSP    (258)
#define DISP_VSW    (10)	//
#define DISP_VDP    (240)	//

#define DISP_DCM1   (0x00000E00)
#define DISP_DCM3   (0x00000100)

///////////////////////////////////////
#elif  (CHOOSE_LCD == LCD_TV070WVM_888_7_0)
#if  1
#define DISP_HTP    (848)
#define DISP_HSP    (842)
#define DISP_HSW    (3)
#define DISP_HDP    (800)	//
#define DISP_VTR    (532)	//
#define DISP_VSP    (525)
#define DISP_VSW    (5)	//
#define DISP_VDP    (480)	//

#define DISP_DCM1   (0x0000300)
#define DISP_DCM3   (0x00000100)
#endif
//////////////////////////////////////////////
#elif (CHOOSE_LCD == LCD_DD070IA_888_7_0)

#define DISP_HTP    (1000)
#define DISP_HSP    (848)
#define DISP_HSW    (52)
#define DISP_HDP    (800)
#define DISP_VTR    (600)
#define DISP_VSP    (504)
#define DISP_VSW    (12)
#define DISP_VDP    (480)

#define DISP_DCM1   (0x00000200)
#define DISP_DCM3   (0x000)
//////////////////////////////////////////////
#elif (CHOOSE_LCD == LCD_CLAA070LFA1_888_7_0)

#define DISP_HTP    (1108)
#define DISP_HSP    (846)
#define DISP_HSW    (240)
#define DISP_HDP    (800)
#define DISP_VTR    (540)
#define DISP_VSP    (503)
#define DISP_VSW    (32)
#define DISP_VDP    (480)

#define DISP_DCM1   (0x00000200)
#define DISP_DCM3   (0x0000)
//////////////////////////////////////////////




#endif
//////////////////////////////////////////


#endif /* GDC_QVGA */

/*========================================================================================================================
Remarks: The modification of the following display clock timing parameter requires rebuild "DispLibAPIL01R02" library for activation.
=======================================================================================================================*/
#ifdef GDC_VGA
/*  Display set param (640x480, clock=108MHz) */
/* VGA */
#define DISP_HTP    (859)
#define DISP_HSP    (700)
#define DISP_HSW    (96)
#define DISP_HDP    (640)
#define DISP_VTR    (525)
#define DISP_VSP    (490)
#define DISP_VSW    (2)
#define DISP_VDP    (480)
#define DISP_DCM1   (0x00000300)
#define DISP_DCM3   (0x100)
#endif /* GDC_VGA */

#endif /* _SAMPLE_COMMON_H_ */
